1. Field of the Invention
The invention relates to a semiconductor device, and more particularly to a high frequency and high speed Schottky gate field effect transistor.
2. Description of the Related Art
Improvements and developments of high frequency and high speed field effect transistors made of compound semiconductors such as InP, InGaAs or other compound semiconductors are very important. High electron mobility field effect transistor showing high frequency and high speed performances have a Schottky gate contact, one of which is disclosed in IEEE Electron Device Letters vol. 9, pp-647, 1988. Namely, a gate electrode made of a metal has to be provided directly on a semiconductor layer so that the gate electrode is electrically separated from the semiconductor layers through the Schottky barrier. As well known, a semiconductor-metal contact or Schottky contact provides a conduction band discontinuity which serves as a potential barrier or Schottky barrier which prevents electrons acting as carriers to flow across the Schottky contact from the metal toward the semiconductor. A sufficient height of the Schottky barrier is necessary to suppress a gate leakage current or to suppress electrons to flow across the Schottky contact from the metal toward the semiconductor.
Typical one of conventional Schottky gate field effect transistor will be described with reference to FIG. 1.
The conventional Schottky gate field effect transistor has a semi-insulating InP substrate 90. A non-doped InAlAs buffer layer 91 is formed on the InP substrate 90. A non-doped InGaAs channel layer 92 is formed on the buffer layer 91. A non-doped InAlAs spacer layer 93a is formed on the channel layer 92. An n-doped InAlAs donor layer 93b is formed on the spacer layer 93a. A non-doped InAlAs Schottky barrier layer 93c is formed on the donor layer 93b. An n-doped InGaAs cap layer 94 with a recess is formed on the Schottky barrier layer 93c. The above layers may be grown by molecular beam epitaxy. The recess in the cap layer 94 may be formed by recess etching. Source and drain electrodes 95s and 95d may be formed on the cap layer 94 by evaporation. A Schottky gate electrode 96 may be formed in the recess on the Schottky barrier layer 93c. A two dimensional electron gas is caused in the channel layer 92 at adjacent regions to the interface with the spacer layer in which carriers or electrons are able to move at a high speed in the two dimensional space.
Although the non-doped InAlAs layer is provided to suppress a gate leakage current, a Schottky barrier height is approximately 0.6 eV which seems insufficient to suppress a gate leakage current. Much more high Schottky barrier is required to realize a sufficient suppression of the gate leakage current or to suppress electrons acting as carriers to move across the Schottky contact surface from the metal region of the gate electrode into the semiconductor region.
To combat the above problem as to the gate leakage current, it was proposed to insert a Schottky barrier layer having a larger energy band gap to reduce a gate leakage current. The field effect transistor having a preferable Schottky gate structure with a high potential barrier to reduce a gate leakage current would, however, be engaged with alternative serious problem as described below. Providing the above preferable Schottky barrier structure in the field effect transistor results in the increase of resistance between the cap layer and the channel layer thereby any high frequency and high speed performance is no longer obtainable. Namely, providing the preferable Schottky barrier structure to suppress the gate leakage current results in a reduction of a probability in a tunneling of electrons between the cap layer and the donor layer through the Schootky barrier with a large height and a sufficient thickness necessary for suppressing the gate leakage current.
It would, therefore, be required to develop a novel Scottky gate field effect transistor possessing not only a preferable Schottky barrier structure to suppress any gate leakage current but also a sufficiently reduced resistance between the cap layer and the channel layer to permit the transistor to exhibit a high frequency and high speed performance.